Invention Grant
US08832332B2 Packet processing apparatus 有权
分组处理装置

Packet processing apparatus
Abstract:
By referring to a receiving connection information table stored in a memory, a receiving assignment CPU assigns packets to parallel processing CPUs in such a manner that the packets received from the same connection are subjected to a receiving process by a corresponding parallel processing CPU. Each parallel processing CPU identifies the input QoS of a packet and notifies a QoS processing CPU, corresponding to that identified input QoS, of the packet. Each QoS processing CPU is arranged so that it corresponds to a QoS processing queue group in the memory and performs a QoS process on this QoS processing queue group.
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