A system for controlling a storage device. A semiconductor chip of the storage device, includes a first memory. The first memory corresponds to a first type of memory, is configured to perform random access memory functions, and is not configured to perform direct memory access functions. A second memory external to the semiconductor chip is configured to interface with the semiconductor chip. The second memory corresponds to a second type of memory that is different than the first type of memory, is configured to perform direct memory access functions, and is not configured to perform random access memory function. The second memory includes a memory cell and an interface configured to interface between components of the second memory including the memory cell and the semiconductor chip.