Invention Grant
- Patent Title: Bit error rate based wear leveling for solid state drive memory
- Patent Title (中): 固态硬盘存储器的基于误码率的磨损均衡
-
Application No.: US13355050Application Date: 2012-01-20
-
Publication No.: US08832506B2Publication Date: 2014-09-09
- Inventor: Thomas J. Griffin , Dustin J. Vanstee
- Applicant: Thomas J. Griffin , Dustin J. Vanstee
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Margaret McNamara
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G11C29/00 ; G01R31/28 ; H03M13/00 ; G11C16/34 ; H04L1/20 ; G06F11/16 ; G01R31/317 ; G11C11/406 ; G11C16/16 ; G11C29/50 ; G11C29/42 ; G11C16/14 ; G11C16/10 ; G06F11/10
Abstract:
According to exemplary embodiments, a system, method, and computer program product are provided for BER-based wear leveling in a SSD. A block-level BER value for a block in the SSD is determined. An adjusted PE cycle count for the block is incremented or decremented based on the block-level BER value. Wear leveling is then performed in the SSD based on the adjusted PE cycle count.
Public/Granted literature
- US20130191700A1 BIT ERROR RATE BASED WEAR LEVELING FOR SOLID STATE DRIVE MEMORY Public/Granted day:2013-07-25
Information query
