Invention Grant
US08832525B2 Memory controller with low density parity check code decoding capability and relevant memory controlling method
有权
具有低密度奇偶校验码解码能力和相关存储器控制方式的存储器控制器
- Patent Title: Memory controller with low density parity check code decoding capability and relevant memory controlling method
- Patent Title (中): 具有低密度奇偶校验码解码能力和相关存储器控制方式的存储器控制器
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Application No.: US13676822Application Date: 2012-11-14
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Publication No.: US08832525B2Publication Date: 2014-09-09
- Inventor: Tsung-Chieh Yang
- Applicant: Silicon Motion, Inc.
- Applicant Address: TW Zhubei, Hsinchu County
- Assignee: Silicon Motion, Inc.
- Current Assignee: Silicon Motion, Inc.
- Current Assignee Address: TW Zhubei, Hsinchu County
- Agency: Birch, Stewart, Kolasch & Birch, LLP
- Priority: TW100141716A 20111115
- Main IPC: H03M13/00
- IPC: H03M13/00 ; H03M13/11 ; H03M13/37
Abstract:
A memory controller includes a memory access circuit and an LDPC decoding circuit. The memory access circuit reads the hard information of a first code word and a second code word from a memory device. The LDPC decoding circuit decodes the first code word according to the hard information of the first code word. When the LDPC decoding circuit does not decode the first code word successfully, the LDPC decoding circuit configures the memory access circuit to read the soft information of the first code word and the second code word, and decodes the first code word and the second code word according to the soft information of the first code word and the second code word.
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