Invention Grant
- Patent Title: Technology mapping for threshold and logic gate hybrid circuits
- Patent Title (中): 门限逻辑门混合电路的技术映射
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Application No.: US13903424Application Date: 2013-05-28
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Publication No.: US08832614B2Publication Date: 2014-09-09
- Inventor: Sarma Vrudhula , Niranjan Kulkarni
- Applicant: Sarma Vrudhula , Niranjan Kulkarni
- Applicant Address: US AZ Scottsdale
- Assignee: Arizona Board of Regents, a body corporate of the State of Arizona, acting for and on behalf of Arizona State University
- Current Assignee: Arizona Board of Regents, a body corporate of the State of Arizona, acting for and on behalf of Arizona State University
- Current Assignee Address: US AZ Scottsdale
- Agency: Withrow & Terranova, P.L.L.C.
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F17/10
Abstract:
A method of mapping threshold gate cells into a Boolean network is disclosed. In one embodiment, cuts are enumerated within the Boolean network. Next, a subset of the cuts within the Boolean network that are threshold is identified. To minimize power, cuts in the subset of the cuts are selected.
Public/Granted literature
- US20130339914A1 TECHNOLOGY MAPPING FOR THRESHOLD AND LOGIC GATE HYBRID CIRCUITS Public/Granted day:2013-12-19
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