A method and device determine FET gate resistance based on both polysilicon resistance and the resistance values of wires and contacts connected to the gate node, plus the fraction of the electric current in each wire segment and in each contact and the path length of electric current in polysilicon. A new gate resistance expression (i.e., a master equation) is used for total gate resistance, which is the sum of core gate resistance and the resistance of wires and contacts connecting polysilicon and a gate node. When there are two or more paths for electric current going from polysilicon to the gate node, the total resistance also depends on the direction and path length of electric current in polysilicon, and the method and device next determine the fraction of electric current in each path by minimizing total resistance with respect to the fractions of the electric current in each path.