Invention Grant
US08835217B2 Device packaging with substrates having embedded lines and metal defined pads
有权
具有嵌入式线路和金属限定衬垫的衬底的器件封装
- Patent Title: Device packaging with substrates having embedded lines and metal defined pads
- Patent Title (中): 具有嵌入式线路和金属限定衬垫的衬底的器件封装
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Application No.: US12975934Application Date: 2010-12-22
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Publication No.: US08835217B2Publication Date: 2014-09-16
- Inventor: Mark S Hlad , Islam A Salama , Mihir K Roy , Tao Wu , Yueli Liu , Kyu Oh Lee
- Applicant: Mark S Hlad , Islam A Salama , Mihir K Roy , Tao Wu , Yueli Liu , Kyu Oh Lee
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L23/02
Abstract:
Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.
Public/Granted literature
- US20120161330A1 DEVICE PACKAGING WITH SUBSTRATES HAVING EMBEDDED LINES AND METAL DEFINED PADS Public/Granted day:2012-06-28
Information query
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