Invention Grant
- Patent Title: Low external resistance ETSOI transistors
- Patent Title (中): 低外部电阻ETSOI晶体管
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Application No.: US13606694Application Date: 2012-09-07
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Publication No.: US08835232B2Publication Date: 2014-09-16
- Inventor: Hemanth Jagannathan , Sivananda K. Kanakasabapathy
- Applicant: Hemanth Jagannathan , Sivananda K. Kanakasabapathy
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent Daniel P. Morris
- Main IPC: H01L29/78
- IPC: H01L29/78

Abstract:
A disposable dielectric structure is formed on a semiconductor-on-insulator (SOI) substrate such that all physically exposed surfaces of the disposable dielectric structure are dielectric surfaces. A semiconductor material is selectively deposited on semiconductor surfaces, while deposition of any semiconductor material on dielectric surfaces is suppressed. After formation of at least one gate spacer and source and drain regions, a planarization dielectric layer is deposited and planarized to physically expose a top surface of the disposable dielectric structure. The disposable dielectric structure is replaced with a replacement gate stack including a gate dielectric and a gate conductor portion. Lower external resistance can be provided without impacting the short channel performance of a field effect transistor device.
Public/Granted literature
- US20130217190A1 LOW EXTERNAL RESISTANCE ETSOI TRANSISTORS Public/Granted day:2013-08-22
Information query
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