Invention Grant
- Patent Title: Interconnect barrier structure and method
- Patent Title (中): 互连屏障结构与方法
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Application No.: US13957685Application Date: 2013-08-02
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Publication No.: US08835313B2Publication Date: 2014-09-16
- Inventor: Chen-Hua Yu, I , Wen-Chih Chiou , Tsang-Jiuh Wu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater and Matsil, L.L.P.
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L21/4763 ; H01L23/48 ; H01L23/00 ; H01L21/768
Abstract:
A system and method for forming through substrate vias is provided. An embodiment comprises forming an opening in a substrate and lining the opening with a first barrier layer. The opening is filled with a conductive material and a second barrier layer is formed in contact with the conductive material. The first barrier layer is formed with different materials and different methods of formation than the second barrier layer so that the materials and methods may be tuned to maximize their effectiveness within the device.
Public/Granted literature
- US20130316528A1 Interconnect Barrier Structure and Method Public/Granted day:2013-11-28
Information query
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