Invention Grant
- Patent Title: Methods to reduce the critical dimension of semiconductor devices and related semiconductor devices
- Patent Title (中): 减少半导体器件和相关半导体器件临界尺寸的方法
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Application No.: US13619905Application Date: 2012-09-14
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Publication No.: US08836083B2Publication Date: 2014-09-16
- Inventor: Baosuo Zhou
- Applicant: Baosuo Zhou
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: TraskBritt
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L21/311 ; H01L21/308 ; H01L21/033
Abstract:
A method of forming features on a target layer. The features have a critical dimension that is triple- or quadruple-reduced compared to the critical dimension of portions of a resist layer used as a mask. An intermediate layer is deposited over a target layer and the resist layer is formed over the intermediate layer. After patterning the resist layer, first spacers are formed on sidewalls of remaining portions of the resist layer, masking portions of the intermediate layer. Second spacers are formed on sidewalls of the portions of the intermediate layer. After removing the portions of the intermediate layer, the second spacers are used as a mask to form the features on the target layer. Integrated circuit devices are also disclosed.
Public/Granted literature
- US20130009283A1 METHODS TO REDUCE THE CRITICAL DIMENSION OF SEMICONDUCTOR DEVICES AND RELATED SEMICONDUCTOR DEVICES Public/Granted day:2013-01-10
Information query
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