Described herein is a semiconductor integrated device assembly, which envisages: a package defining an internal space; a first die including semiconductor material; and a second die, distinct from the first die, also including semiconductor material; the first die and the second die are coupled to an inner surface of the package facing the internal space. The second die is shaped so as to partially overlap the first die, above the inner surface, with a portion suspended in cantilever fashion above the first die, by an overlapping distance.