Invention Grant
- Patent Title: Vertical mount package and wafer level packaging therefor
- Patent Title (中): 垂直安装封装和晶圆级封装
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Application No.: US13438370Application Date: 2012-04-03
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Publication No.: US08836132B2Publication Date: 2014-09-16
- Inventor: Xiaojie Xue
- Applicant: Xiaojie Xue
- Applicant Address: US MA Norwood
- Assignee: Analog Devices, Inc.
- Current Assignee: Analog Devices, Inc.
- Current Assignee Address: US MA Norwood
- Agency: Knobbe, Martens, Olson & Bear LLP
- Main IPC: H01L23/48
- IPC: H01L23/48

Abstract:
Vertical mount packages and methods for making the same are disclosed. A method for manufacturing a vertical mount package includes providing a device substrate with a plurality of device regions on a front surface, and a plurality of through-wafer vias. MEMS devices or integrated circuits are formed or mounted onto the device regions. A capping substrate having recesses is mounted over the device substrate, enclosing the device regions within cavities defined by the recesses. A plurality of aligned through-wafer contacts extend through the capping substrate and the device substrate. The device substrate and capping substrate can be singulated by cutting through the aligned through-wafer contacts, with the severed through-wafer contacts forming vertical mount leads. A vertical mount package includes a device sealed between a device substrate and a capping substrate. At least of the side edges of the package includes exposed conductive elements for vertical mount leads.
Public/Granted literature
- US20130256896A1 VERTICAL MOUNT PACKAGE AND WAFER LEVEL PACKAGING THEREFOR Public/Granted day:2013-10-03
Information query
IPC分类: