Invention Grant
- Patent Title: Clock selection circuit and method
- Patent Title (中): 时钟选择电路及方法
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Application No.: US14175822Application Date: 2014-02-07
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Publication No.: US08836379B2Publication Date: 2014-09-16
- Inventor: Surendra Guntur , Ghiath Al-kadi , Rinze Ida Mechtildis Peter Meijer , Jan Hoogerbrugge , Hamed Fatemi
- Applicant: NXP B.V.
- Applicant Address: NL Eindhoven
- Assignee: NXP B.V.
- Current Assignee: NXP B.V.
- Current Assignee Address: NL Eindhoven
- Priority: EP13153740 20130201
- Main IPC: H03K17/00
- IPC: H03K17/00 ; G06F1/08

Abstract:
The invention provides a clock select circuit and method which uses feedback arrangements between latches in different branches, with each branch for coupling an associated clock signal to the circuit output. An override circuit is provided in one of the feedback arrangements for preventing a latching delay in that feedback arrangement. This enables rapid switching between clocks in both directions.
Public/Granted literature
- US20140223220A1 CLOCK SELECTION CIRCUIT AND METHOD Public/Granted day:2014-08-07
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