Invention Grant
- Patent Title: Guarded electrical overstress protection circuit
- Patent Title (中): 保护电气过载保护电路
-
Application No.: US12647067Application Date: 2009-12-24
-
Publication No.: US08837099B2Publication Date: 2014-09-16
- Inventor: Michael Coln , Gary Carreau , Yoshinori Kusuda
- Applicant: Michael Coln , Gary Carreau , Yoshinori Kusuda
- Applicant Address: US MA Norwood
- Assignee: Analog Devices, Inc.
- Current Assignee: Analog Devices, Inc.
- Current Assignee Address: US MA Norwood
- Agency: Kenyon & Kenyon, LLP
- Main IPC: H02H9/00
- IPC: H02H9/00 ; H01L27/02

Abstract:
Disclosed embodiments are directed to an electrical overstress protection circuit. The electrical overstress protection circuit may include an intermediate node receiving a reference voltage, a first pair of clamp devices, having opposite polarity, clamping an input signal line to the intermediate node, and a second pair of clamp devices, each clamping the intermediate node to one of two reference potentials. The electrical overstress protection circuit may also include a filter connected to the intermediate node to reduce noise at the intermediate node.
Public/Granted literature
- US20110038083A1 GUARDED ELECTRICAL OVERSTRESS PROTECTION CIRCUIT Public/Granted day:2011-02-17
Information query