Invention Grant
US08837251B2 Semiconductor device with low voltage programming/erasing operation
有权
具有低电压编程/擦除操作的半导体器件
- Patent Title: Semiconductor device with low voltage programming/erasing operation
- Patent Title (中): 具有低电压编程/擦除操作的半导体器件
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Application No.: US13122732Application Date: 2009-10-05
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Publication No.: US08837251B2Publication Date: 2014-09-16
- Inventor: Takayuki Kawahara , Riichiro Takemura , Kazuo Ono
- Applicant: Takayuki Kawahara , Riichiro Takemura , Kazuo Ono
- Applicant Address: JP Tokyo
- Assignee: Hitachi, Ltd.
- Current Assignee: Hitachi, Ltd.
- Current Assignee Address: JP Tokyo
- Agency: Miles & Stockbridge P.C.
- Priority: JP2008-259206 20081006
- International Application: PCT/JP2009/067354 WO 20091005
- International Announcement: WO2010/041632 WO 20100415
- Main IPC: G11C8/00
- IPC: G11C8/00 ; G11C11/16 ; G11C11/4094 ; G11C11/4097 ; G11C7/12 ; G11C7/18

Abstract:
An array configuration capable of supplying a necessary and sufficient current in a small area is achieved and a reference cell configuration suitable to temperature characteristics of a TMR element is achieved. In a memory using inversion of spin transfer switching, a plurality of program drivers are arranged separately along one global bit line, and one sense amplifier is provided to one global bit line. A reference cell to which “1” and “0” are programmed is shared by two arrays and a sense amplifier.
Public/Granted literature
- US20110194361A1 SEMICONDUCTOR DEVICE Public/Granted day:2011-08-11
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