Invention Grant
- Patent Title: Power state transition verification for electronic design
- Patent Title (中): 电子设计的电力状态转换验证
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Application No.: US13600074Application Date: 2012-08-30
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Publication No.: US08839164B2Publication Date: 2014-09-16
- Inventor: Paparao S. Kavalipati , Andrew Seawright
- Applicant: Paparao S. Kavalipati , Andrew Seawright
- Applicant Address: US OR Wilsonville
- Assignee: Mentor Graphics Corporation
- Current Assignee: Mentor Graphics Corporation
- Current Assignee Address: US OR Wilsonville
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Various implementations of the invention may be applied to generate an auxiliary verification statement. The auxiliary verification statement defines properties that check if the power domains are active at appropriate times is generated. Particularly, the auxiliary verification statement checks to ensure that power domain transitions do not interfere with the operation of the device design. With various implementations of the invention, an auxiliary verification statement may be generated by first determining a set of properties instantiated in a verification statement and then synthesizing the auxiliary verification statement based upon the determined properties, the corresponding device design and the power domains. In some implementations, the auxiliary verification statement instantiates properties that check if the power domains related to the properties in the verification statement are active when the verifications statement is exercised. In various implementations, this is accomplished by substituting select ones of the properties in the verification statement with select properties corresponding to the power domain.
Public/Granted literature
- US20130232460A1 Power State Transition Verification For Electronic Design Public/Granted day:2013-09-05
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