Invention Grant
- Patent Title: Placement and area adjustment for hierarchical groups in printed circuit board design
- Patent Title (中): 印刷电路板设计中层次组的放置和面积调整
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Application No.: US13755587Application Date: 2013-01-31
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Publication No.: US08839174B2Publication Date: 2014-09-16
- Inventor: Gerald P. Suiter
- Applicant: Mentor Graphics Corporation
- Applicant Address: US OR Wilsonville
- Assignee: Mentor Graphics Corporation
- Current Assignee: Mentor Graphics Corporation
- Current Assignee Address: US OR Wilsonville
- Agency: Banner & Witcoff, Ltd.
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Aspects of the invention are directed towards placing components within a layout design for a PCB. More specifically, various implementations of the invention provide methods and apparatuses that can dynamically adjust the shape or placement of component groups during an HGP process. With some implementations of the invention, an HGP process for planning the layout of a PCB is provided. Furthermore, component groups, which conflict, geographically, with either another component group or some other object within the layout design are allowed to be placed during the planning process. Subsequently, the placement locations for one or both of the conflicting component groups are adjusted to resolve the conflict. In some implementations, the geometric boundary, or footprint, of one or both of the component groups is adjusted to resolve the conflict.
Public/Granted literature
- US20130198708A1 Placement and Area Adjustment for Hierarchical Groups in Printed Circuit Board Design Public/Granted day:2013-08-01
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