A thin film transistor array panel includes: a gate line and a storage electrode on a substrate and separated from each other; a gate insulating layer covering the gate line and the storage electrode; a data line crossing the gate line and being on the gate insulating layer; a thin film transistor formed at a crossing region of the gate line and the data line, and including a gate electrode, a source electrode, and a drain electrode; a passivation layer exposing a portion of the drain electrode and formed on the thin film transistor and the data line; and a pixel electrode contacting the drain electrode and overlapping the storage electrode with the gate insulating layer interposed therebetween.