Invention Grant
US08841682B2 Transistors with a gate insulation layer having a channel depleting interfacial charge and related fabrication methods
有权
具有栅极绝缘层的晶体管具有通道耗尽的界面电荷和相关的制造方法
- Patent Title: Transistors with a gate insulation layer having a channel depleting interfacial charge and related fabrication methods
- Patent Title (中): 具有栅极绝缘层的晶体管具有通道耗尽的界面电荷和相关的制造方法
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Application No.: US12548763Application Date: 2009-08-27
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Publication No.: US08841682B2Publication Date: 2014-09-23
- Inventor: Sarit Dhar , Sei-Hyung Ryu
- Applicant: Sarit Dhar , Sei-Hyung Ryu
- Applicant Address: US NC Durham
- Assignee: Cree, Inc.
- Current Assignee: Cree, Inc.
- Current Assignee Address: US NC Durham
- Agency: Myers Bigel Sibley & Sajovec, P.A.
- Main IPC: H01L29/161
- IPC: H01L29/161 ; H01L21/04 ; H01L29/78 ; H01L29/16 ; H01L29/66 ; H01L29/51
Abstract:
A metal-insulator-semiconductor field-effect transistor (MISFET) includes a SiC layer with source and drain regions of a first conductivity type spaced apart therein. A first gate insulation layer is on the SiC layer and has a net charge along an interface with the SiC layer that is the same polarity as majority carriers of the source region. A gate contact is on the first gate insulation layer over a channel region of the SiC layer between the source and drain regions. The net charge along the interface between the first gate insulation layer and the SiC layer may deplete majority carriers from an adjacent portion of the channel region between the source and drain regions in the SiC layer, which may increase the threshold voltage of the MISFET and/or increase the electron mobility therein.
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