Invention Grant
- Patent Title: Semiconductor device comprising a capacitor and an electrical connection via and fabrication method
- Patent Title (中): 包括电容器和电连接通孔及其制造方法的半导体器件
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Application No.: US13298735Application Date: 2011-11-17
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Publication No.: US08841748B2Publication Date: 2014-09-23
- Inventor: Sylvain Joblot , Alexis Farcy , Jean-Francois Carpentier , Pierre Bar
- Applicant: Sylvain Joblot , Alexis Farcy , Jean-Francois Carpentier , Pierre Bar
- Applicant Address: FR Montrogue
- Assignee: STMicroelectronics SA
- Current Assignee: STMicroelectronics SA
- Current Assignee Address: FR Montrogue
- Agency: Gardere Wynne Sewell LLP
- Priority: FR1059917 20101130
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L23/58 ; H01L21/768 ; H01L23/48 ; H01L23/522

Abstract:
A dielectric wafer has, on top of its front face, a front electrical connection including an electrical connection portion. A blind hole passes through from a rear face of the wafer to at least partially reveal a rear face of the electrical connection portion. A through capacitor is formed in the blind hole. The capacitor includes a first conductive layer covering the lateral wall and the electrical connection portion (forming an outer electrode), a dielectric intermediate layer covering the first conductive layer (forming a dielectric membrane), and a second conductive layer covering the dielectric intermediate layer (forming an inner electrode). A rear electrical connection is made to the inner electrode.
Public/Granted literature
- US20120133020A1 SEMICONDUCTOR DEVICE COMPRISING A CAPACITOR AND AN ELECTRICAL CONNECTION VIA AND FABRICATION METHOD Public/Granted day:2012-05-31
Information query
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