Invention Grant
- Patent Title: Multi-chip module with stacked face-down connected dies
- Patent Title (中): 具有堆叠面朝下连接的模具的多芯片模块
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Application No.: US13092376Application Date: 2011-04-22
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Publication No.: US08841765B2Publication Date: 2014-09-23
- Inventor: Belgacem Haba , Ilyas Mohammed , Piyush Savalia
- Applicant: Belgacem Haba , Ilyas Mohammed , Piyush Savalia
- Applicant Address: US CA San Jose
- Assignee: Tessera, Inc.
- Current Assignee: Tessera, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Lerner, David, Littenberg, Krumholz & Mentlik, LLP
- Main IPC: H01L23/34
- IPC: H01L23/34

Abstract:
A microelectronic assembly can include a substrate having first and second surfaces, at least two logic chips overlying the first surface, and a memory chip having a front surface with contacts thereon, the front surface of the memory chip confronting a rear surface of each logic chip. The substrate can have conductive structure thereon and terminals exposed at the second surface for connection with a component. Signal contacts of each logic chip can be directly electrically connected to signal contacts of the other logic chips through the conductive structure of the substrate for transfer of signals between the logic chips. The logic chips can be adapted to simultaneously execute a set of instructions of a given thread of a process. The contacts of the memory chip can be directly electrically connected to the signal contacts of at least one of the logic chips through the conductive structure of the substrate.
Public/Granted literature
- US20120267777A1 MULTI-CHIP MODULE WITH STACKED FACE-DOWN CONNECTED DIES Public/Granted day:2012-10-25
Information query
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