Invention Grant
US08843732B2 Mechanism for detecting a no-processor swap condition and modification of high speed bus calibration during boot
有权
用于检测无处理器交换条件的机制和引导期间高速总线校准的修改
- Patent Title: Mechanism for detecting a no-processor swap condition and modification of high speed bus calibration during boot
- Patent Title (中): 用于检测无处理器交换条件的机制和引导期间高速总线校准的修改
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Application No.: US12643108Application Date: 2009-12-21
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Publication No.: US08843732B2Publication Date: 2014-09-23
- Inventor: Mahesh S. Natu , John V. Lovelace , Rajesh P. Banginwar
- Applicant: Mahesh S. Natu , John V. Lovelace , Rajesh P. Banginwar
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: G06F9/24
- IPC: G06F9/24 ; G06F15/177 ; G06F1/24 ; G06F21/85 ; G06F21/57 ; G06F21/74

Abstract:
Memory channel training parameters are function of electrical characteristics of memory devices, processor(s) and memory channel(s). Training steps can be skipped if the BIOS can determine that the memory devices, motherboard and processor have not changed since the last boot. Memory devices contain a serial number for tracking purposes and most motherboards contain a serial number. Many processors do not provide a mechanism by which the BIOS can track the processor. Described herein are techniques that allow the BIOS to track a processor and detect a swap without violating privacy/security requirements.
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