Invention Grant
- Patent Title: Providing a multi-phase lockstep integrity reporting mechanism
- Patent Title (中): 提供多阶段锁步完整性报告机制
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Application No.: US13925991Application Date: 2013-06-25
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Publication No.: US08844021B2Publication Date: 2014-09-23
- Inventor: Ned M. Smith , Vedvyas Shanbhogue , Geoffrey S. Strongin , Willard M. Wiseman , David W. Grawrock
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: G06F21/44
- IPC: G06F21/44 ; H04L29/08 ; G06F21/57 ; H04L29/06

Abstract:
In one embodiment, a processor can enforce a blacklist and validate, according to a multi-phase lockstep integrity protocol, a device coupled to the processor. Such enforcement may prevent the device from accessing one or more resources of a system prior to the validation. The blacklist may include a list of devices that have not been validated according to the multi-phase lockstep integrity protocol. Other embodiments are described and claimed.
Public/Granted literature
- US20130283369A1 Providing A Multi-Phase Lockstep Integrity Reporting Mechanism Public/Granted day:2013-10-24
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