Invention Grant
- Patent Title: Integrated circuit with multi recessed shallow trench isolation
- Patent Title (中): 集成电路具有多凹槽浅沟槽隔离
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Application No.: US13910757Application Date: 2013-06-05
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Publication No.: US08846465B2Publication Date: 2014-09-30
- Inventor: Tsung-Lin Lee , Chang-Yun Chang
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L21/337
- IPC: H01L21/337 ; H01L21/762

Abstract:
A system and method for forming multi recessed shallow trench isolation structures on substrate of an integrated circuit is provided. An integrated circuit includes a substrate, at least two shallow trench isolation (STI) structures formed in the substrate, an oxide fill disposed in the at least two STI structures, and semiconductor devices disposed on the oxide fill in the at least two STI structures. A first STI structure is formed to a first depth and a second STI structure is formed to a second depth. The oxide fill fills the at least two STI structures, and the first depth and the second depth are based on semiconductor device characteristics of semiconductor devices disposed thereon.
Public/Granted literature
- US20130267075A1 Integrated Circuit with Multi Recessed Shallow Trench Isolation Public/Granted day:2013-10-10
Information query
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