Fabrication method of trenched power semiconductor device with source trench

Invention Grant

US08846469B2 Fabrication method of trenched power semiconductor device with source trench 有权

Title translation: 具有沟槽沟槽功率半导体器件的制造方法

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Patent Title: Fabrication method of trenched power semiconductor device with source trench
Patent Title (中): 具有沟槽沟槽功率半导体器件的制造方法
Application No.: US13470302

Application Date: 2012-05-12
Publication No.: US08846469B2

Publication Date: 2014-09-30
Inventor: Chun Ying Yeh , Hsiu Wen Hsu
Applicant: Chun Ying Yeh , Hsiu Wen Hsu
Applicant Address: TW New Taipei
Assignee: Great Power Semiconductor Corp.
Current Assignee: Great Power Semiconductor Corp.
Current Assignee Address: TW New Taipei
Agency: Li & Cai Intellectual Property (USA) Office
Priority: TW100121504A 20110620
Main IPC: H01L21/8242
IPC: H01L21/8242 ; H01L29/78 ; H01L29/417 ; H01L29/40 ; H01L29/66 ; H01L21/265 ; H01L29/10

Fabrication method of trenched power semiconductor device with source trench

Abstract:

A fabrication method of a trenched power semiconductor device with source trench is provided. Firstly, at least two gate trenches are formed in a base. Then, a dielectric layer and a polysilicon structure are sequentially formed in the gate trench. Afterward, at least a source trench is formed between the neighboring gate trenches. Next, the dielectric layer and a second polysilicon structure are sequentially formed in the source trench. The second polysilicon structure is located in a lower portion of the source trench. Then, the exposed portion of the dielectric layer in the source trench is removed to expose a source region and a body region. Finally, a conductive structure is filled into the source trench to electrically connect the second polysilicon structure, the body region, and the source region.

Abstract(Chinese):

提供了具有源沟槽的沟槽功率半导体器件的制造方法。首先，在基底中形成至少两个栅极沟槽。然后，在栅极沟槽中依次形成电介质层和多晶硅结构。之后，在相邻的栅极沟槽之间形成至少一个源极沟槽。接下来，电介质层和第二多晶硅结构依次形成在源沟槽中。第二多晶硅结构位于源沟槽的下部。然后，去除源沟槽中的电介质层的暴露部分以暴露源区和体区。最后，将导电结构填充到源沟槽中以电连接第二多晶硅结构，体区和源极区。

Public/Granted literature

US20120322217A1 FABRICATION METHOD OF TRENCHED POWER SEMICONDUCTOR DEVICE WITH SOURCE TRENCH Public/Granted day:2012-12-20

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IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺
H01L21/8239	........存储器结构
H01L21/8242	.........动态随机存取存储结构（DRAM）