Invention Grant
US08847302B2 Vertical NAND device with low capacitance and silicided word lines
有权
具有低电容和硅化字线的垂直NAND器件
- Patent Title: Vertical NAND device with low capacitance and silicided word lines
- Patent Title (中): 具有低电容和硅化字线的垂直NAND器件
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Application No.: US13443287Application Date: 2012-04-10
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Publication No.: US08847302B2Publication Date: 2014-09-30
- Inventor: Johann Alsmeier , Peter Rabkin
- Applicant: Johann Alsmeier , Peter Rabkin
- Applicant Address: US TX Plano
- Assignee: Sandisk Technologies Inc.
- Current Assignee: Sandisk Technologies Inc.
- Current Assignee Address: US TX Plano
- Agency: The Marbury Law Group PLLC
- Main IPC: H01L29/788
- IPC: H01L29/788
Abstract:
A three dimensional memory device including a substrate and a semiconductor channel. At least one end portion of the semiconductor channel extends substantially perpendicular to a major surface of the substrate. The device also includes at least one charge storage region located adjacent to semiconductor channel and a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate. The plurality of control gate electrodes include at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level. Each of the plurality of control gate electrodes includes a first edge surface which is substantially free of silicide, the first edge surface facing the semiconductor channel and the at least one charge storage region and a silicide located on remaining surfaces of the control gate electrode.
Public/Granted literature
- US20130264631A1 VERTICAL NAND DEVICE WITH LOW CAPACITANCE AND SILICIDED WORD LINES Public/Granted day:2013-10-10
Information query
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