A dual polysilicon gate of a semiconductor device includes a substrate having a first region, a second region, and a third region, and a channel region with a protrusion structure formed in the substrate of the first region, a gate insulating layer formed over the substrate, a first polysilicon layer filling the channel region, and formed over the gate insulating layer of the first and second regions, a second polysilicon layer formed over the gate insulating layer of the third region, and an insulating layer doped with an impurity, and disposed inside the first polysilicon layer in the channel region.