Invention Grant
US08847331B2 Semiconductor chip including region having cross-coupled transistor configuration with offset electrical connection areas on gate electrode forming conductive structures and at least two different inner extension distances of gate electrode forming conductive structures 有权
半导体芯片包括具有交叉耦合晶体管配置的区域,在栅电极上形成具有导电结构的偏移电连接区域和形成导电结构的栅电极的至少两个不同的内延伸距离

  • Patent Title: Semiconductor chip including region having cross-coupled transistor configuration with offset electrical connection areas on gate electrode forming conductive structures and at least two different inner extension distances of gate electrode forming conductive structures
  • Patent Title (中): 半导体芯片包括具有交叉耦合晶体管配置的区域,在栅电极上形成具有导电结构的偏移电连接区域和形成导电结构的栅电极的至少两个不同的内延伸距离
  • Application No.: US14273483
    Application Date: 2014-05-08
  • Publication No.: US08847331B2
    Publication Date: 2014-09-30
  • Inventor: Scott T. BeckerJim MaliCarole Lambert
  • Applicant: Tela Innovations, Inc.
  • Applicant Address: US CA Los Gatos
  • Assignee: Tela Innovations, Inc.
  • Current Assignee: Tela Innovations, Inc.
  • Current Assignee Address: US CA Los Gatos
  • Agency: Martine Penilla Group, LLP
  • Main IPC: H01L27/088
  • IPC: H01L27/088 H01L27/092 G06F17/50 H01L23/538
Semiconductor chip including region having cross-coupled transistor configuration with offset electrical connection areas on gate electrode forming conductive structures and at least two different inner extension distances of gate electrode forming conductive structures
Abstract:
A first linear-shaped conductive structure (LCS) forms a gate electrode (GE) of a first transistor of a first transistor type. A second LCS forms a GE of a first transistor of a second transistor type. A third LCS forms a GE of a second transistor of the first transistor type. A fourth LCS forms a GE of a second transistor of the second transistor type. Each of the first, second, third, and fourth LCS's has a respective electrical connection area. The electrical connection areas of the first and third LCS's are offset from each other. The GE of the first transistor of the first transistor type is electrically connected to the GE of the second transistor of the second transistor type. The GE of the second transistor of the first transistor type is electrically connected to the GE of the first transistor of the second transistor type.
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