A semiconductor apparatus includes: a variable delay unit configured to delay a reference clock signal in response to a delay code and generate a data latch clock signal; a delay amount control unit configured to convert a phase of external data and a phase of the data latch clock signal into first and second codes, respectively, and generate the delay code through a calculation of the first and second codes; and a data receiver configured to latch the external data as internal data in synchronization with the data latch clock signal.