Invention Grant
- Patent Title: Bumpless build-up layer package warpage reduction
- Patent Title (中): 无皱堆积层包装翘曲缩小
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Application No.: US13173327Application Date: 2011-06-30
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Publication No.: US08848380B2Publication Date: 2014-09-30
- Inventor: Pramod Malatkar , Drew W. Delaney
- Applicant: Pramod Malatkar , Drew W. Delaney
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Winkle PLLC
- Main IPC: H05K7/20
- IPC: H05K7/20 ; H01L23/34 ; H01L23/00 ; H01L25/16 ; H01L25/10 ; H01L25/00 ; H01L21/683

Abstract:
The present disclosure relates to the field of fabricating microelectronic packages and the fabrication thereof, wherein a microelectronic device may be formed within a bumpless build-up layer coreless (BBUL-C) microelectronic package and wherein a warpage control structure may be disposed on a back surface of the microelectronic device. The warpage control structure may be a layered structure comprising at least one layer of high coefficient of thermal expansion material, including but not limited to a filled epoxy material, and at least one high elastic modulus material layer, such as a metal layer.
Public/Granted literature
- US20130003319A1 BUMPLESS BUILD-UP LAYER PACKAGE WARPAGE REDUCTION Public/Granted day:2013-01-03
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