Invention Grant
US08848447B2 Nonvolatile semiconductor memory device using write pulses with different voltage gradients
有权
非易失性半导体存储器件使用具有不同电压梯度的写入脉冲
- Patent Title: Nonvolatile semiconductor memory device using write pulses with different voltage gradients
- Patent Title (中): 非易失性半导体存储器件使用具有不同电压梯度的写入脉冲
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Application No.: US13226826Application Date: 2011-09-07
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Publication No.: US08848447B2Publication Date: 2014-09-30
- Inventor: Yasuhiro Shiino , Daisuke Kouno , Shigefumi Irieda , Kenri Nakai , Eietsu Takahashi
- Applicant: Yasuhiro Shiino , Daisuke Kouno , Shigefumi Irieda , Kenri Nakai , Eietsu Takahashi
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2010-211864 20100922
- Main IPC: G11C11/34
- IPC: G11C11/34 ; G11C16/04 ; G11C16/10 ; G11C16/34

Abstract:
A nonvolatile semiconductor memory device in accordance with an embodiment includes: a memory cell array having electrically rewritable nonvolatile memory cells; and a control unit. The control unit performs control of repeating a write operation, a write verify operation, and a step-up operation, the write verify operation being an operation to verify whether data write is completed or not, and the step-up operation being an operation to raise the write pulse voltage if data write is not completed. The control unit, during the write operation, raises a first write pulse voltage with a first gradient, and then raises a second write pulse voltage with a second gradient, thereby executing the write operation, the first write pulse voltage including at least a write pulse voltage generated at first, the second write pulse voltage being generated after the first write pulse voltage, and the second gradient being larger than the first gradient.
Public/Granted literature
- US20120072648A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2012-03-22
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