A memory system may provide for a successful write of a multi-port memory cell (e.g., dual-port 2WR SRAM cell) when it is simultaneously accessed by more than one port. This multi-port memory cell may include at least two independent accesses to the memory cell, where each access may be controlled by an independent wordline signal. Each port may have an independent pair of bitlines. Multiple write circuitry (e.g., double write circuitry) may enable the write driver to drive the input data to more than one pair of bitlines simultaneously.