Invention Grant
- Patent Title: SPDIF clock and data recovery with sample rate converter
- Patent Title (中): SPDIF时钟和采样率转换器的数据恢复
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Application No.: US13800557Application Date: 2013-03-13
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Publication No.: US08848849B1Publication Date: 2014-09-30
- Inventor: Samuel J. Peters , Eric P. Etheridge , Victor Lee Hanson , Alexander C. Stange
- Applicant: Avnera Corporation
- Applicant Address: US OR Beaverton
- Assignee: Avnera Corporation
- Current Assignee: Avnera Corporation
- Current Assignee Address: US OR Beaverton
- Agency: Ater Wynne LLP
- Agent Patrick D. Boyd; Paul B. Heynssens
- Main IPC: H04L7/02
- IPC: H04L7/02

Abstract:
A system and a technique for recovering data from an input data stream without synchronization of an input sampling circuit to the input data stream determines a count of incoming samples (or frames) without generating a signal that is frequency-locked to the input data stream. A first clock is generated comprising a frequency that is greater than or equal to an expected frequency of the input data stream. A sample count is incremented in response to a sample received in the input data stream, and is decremented in response to a second clock signal. The second clock is generated the first clock signal by passing the first clock signal if the sample count of the sample counter does not equal a predetermined sample count value and by blocking the first clock signal if the sample count equals the predetermined sample count value.
Public/Granted literature
- US20140270028A1 SPDIF Clock and Data Recovery With Sample Rate Converter Public/Granted day:2014-09-18
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