Invention Grant
- Patent Title: Operating memory with specified cache address
- Patent Title (中): 具有指定缓存地址的操作内存
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Application No.: US13867897Application Date: 2013-04-22
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Publication No.: US08850119B2Publication Date: 2014-09-30
- Inventor: Theodore T. Pekny , Jeff Yu
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Fletcher Yoder, P.C.
- Main IPC: G06F12/02
- IPC: G06F12/02 ; G06F12/08

Abstract:
Embodiments are provided for operating a memory device by issuing certain instructions to the memory device that specify a cache and/or memory array address where an operation is to occur. One such method may include loading data into a specified address of a cache of the memory device, in which the specified address of the cache of the memory device may be specified by a first program sequence received at an interface of the memory device from a host external to the memory device. The method may also include writing the data from the specified address of the cache of the memory device to a specified address of a memory array of the memory device, in which the specified address of the memory array of the memory device may be specified by a second program sequence received at the interface from the host.
Public/Granted literature
- US20130238846A1 SERIAL INTERFACE NAND Public/Granted day:2013-09-12
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