Invention Grant
- Patent Title: Method of fabricating land grid array semiconductor package
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Application No.: US14177146Application Date: 2014-02-10
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Publication No.: US08860207B2Publication Date: 2014-10-14
- Inventor: Yonggang Jin , Romain Coffy , Jerome Teysseyre
- Applicant: STMicroelectronics Pte Ltd. , STMicroelectronics Grenoble 2 SAS
- Applicant Address: SG Singapore FR Grenoble
- Assignee: STMicroelectronics Pte Ltd,STMicroelectronics Grenoble 2 SAS
- Current Assignee: STMicroelectronics Pte Ltd,STMicroelectronics Grenoble 2 SAS
- Current Assignee Address: SG Singapore FR Grenoble
- Agency: Seed IP Law Group PLLC
- Main IPC: H01L23/34
- IPC: H01L23/34 ; H01L21/00 ; H01R43/16 ; H01L23/498 ; H01L23/36 ; H01L23/31 ; H01L21/768

Abstract:
A fan-out wafer level package is provided with a semiconductor die embedded in a reconstituted wafer. A redistribution layer is positioned over the semiconductor die, and includes a land grid array on a face of the package. A copper heat spreader is formed in the redistribution layer over the die in a same layer as a plurality of electrical traces configured to couple circuit pads of the semiconductor die to respective contact lands of the land grid array. In operation, the heat spreader improves efficiency of heat transfer from the die to the circuit board.
Public/Granted literature
- US20140191387A1 METHOD OF FABRICATING LAND GRID ARRAY SEMICONDUCTOR PACKAGE Public/Granted day:2014-07-10
Information query
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