Invention Grant
- Patent Title: Semiconductor device having redundant word lines and redundant bit lines
- Patent Title (中): 具有冗余字线和冗余位线的半导体器件
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Application No.: US13594679Application Date: 2012-08-24
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Publication No.: US08861292B2Publication Date: 2014-10-14
- Inventor: Tatsuo Sawada
- Applicant: Tatsuo Sawada
- Applicant Address: LU Luxembourg
- Assignee: PSA Luxco S.A.R.L.
- Current Assignee: PSA Luxco S.A.R.L.
- Current Assignee Address: LU Luxembourg
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2011-188825 20110831
- Main IPC: G11C7/00
- IPC: G11C7/00 ; G11C17/16 ; G11C11/408 ; G11C17/18 ; G11C29/00 ; G11C29/44 ; G11C29/02
Abstract:
A semiconductor device includes a memory cell array having short and long sides, a row decoder, a row fuse circuit, a column decoder and a column fuse circuit. The row decoder, the row fuse circuit and the column fuse circuit are arranged along the long side of the memory cell array. The column decoder is arranged along the short side of the memory cell array.
Public/Granted literature
- US20130051160A1 SEMICONDUCTOR DEVICE HAVING REDUNDANT WORD LINES AND REDUNDANT BIT LINES Public/Granted day:2013-02-28
Information query
