Invention Grant
- Patent Title: 3D semiconductor package interposer with die cavity
- Patent Title (中): 具有模腔的3D半导体封装插入器
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Application No.: US13899815Application Date: 2013-05-22
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Publication No.: US08865521B2Publication Date: 2014-10-21
- Inventor: Shin-Puu Jeng , Kim Hong Chen , Shang-Yun Hou , Chao-Wen Shih , Cheng-Chieh Hsieh , Chen-Hua Yu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/30 ; H01L25/00 ; H01L23/498 ; H01L23/13 ; H01L23/00 ; H01L23/367 ; H01L23/42

Abstract:
A 3D semiconductor package using an interposer is provided. In an embodiment, an interposer is provided having a first die electrically coupled to a first side of the interposer and a second die electrically coupled to a second side of the interposer. The interposer is electrically coupled to an underlying substrate, such as a packaging substrate, a high-density interconnect, a printed circuit board, or the like. The substrate has a cavity such that the second die is positioned within the cavity. The use of a cavity may allow smaller conductive bumps to be used, thereby allowing a higher number of conductive bumps to be used. A heat sink may be placed within the cavity to aid in the dissipation of the heat from the second die.
Public/Granted literature
- US20130252378A1 3D Semiconductor Package Interposer with Die Cavity Public/Granted day:2013-09-26
Information query
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