Invention Grant
- Patent Title: Manufacturing method of a semiconductor device and method for creating a layout thereof
- Patent Title (中): 半导体器件的制造方法及其布局的制造方法
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Application No.: US13665803Application Date: 2012-10-31
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Publication No.: US08865583B2Publication Date: 2014-10-21
- Inventor: Kosuke Yanagidaira , Chikaaki Kodama
- Applicant: Kosuke Yanagidaira , Chikaaki Kodama
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2007-320444 20071212
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L27/115 ; H01L23/522 ; H01L27/02 ; H01L21/768 ; H01L21/311

Abstract:
A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.
Public/Granted literature
- US20130164934A1 MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE AND METHOD FOR CREATING A LAYOUT THEREOF Public/Granted day:2013-06-27
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