Invention Grant
US08866023B2 Method and system for reducing trace length and capacitance in a large memory footprint
有权
在大容量内存中减少走线长度和电容的方法和系统
- Patent Title: Method and system for reducing trace length and capacitance in a large memory footprint
- Patent Title (中): 在大容量内存中减少走线长度和电容的方法和系统
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Application No.: US13265323Application Date: 2009-04-17
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Publication No.: US08866023B2Publication Date: 2014-10-21
- Inventor: Rachid M. Kadri , Stephen F. Contreras
- Applicant: Rachid M. Kadri , Stephen F. Contreras
- Applicant Address: US TX Houston
- Assignee: Hewlett-Packard Development Company, L.P.
- Current Assignee: Hewlett-Packard Development Company, L.P.
- Current Assignee Address: US TX Houston
- International Application: PCT/US2009/040997 WO 20090417
- International Announcement: WO2010/120310 WO 20101021
- Main IPC: H05K1/11
- IPC: H05K1/11 ; H05K1/18 ; G11C5/06 ; H05K1/14 ; H05K1/02

Abstract:
A method and system are disclosed to reduce trace length and capacitance in a large memory footprint. When more dual in-line memory module (DIMM) connectors are used per memory channel, the overall bus bandwidth may be affected by trace length and trace capacitance. In order to reduce the overall trace length and trace capacitance, the system and method use a palm tree topology placement, i.e., back-to-back DIMM placement, to place surface mount technology (SMT) DIMM connectors (instead of through-hole connectors) back-to-back in a mirror fashion on each side of a printed circuit board (PCB). The system and method may improve signal propagation time when compared to the commonly used traditional topology placements in which all DIMM connectors are placed on one side of the PCB.
Public/Granted literature
- US20120175160A1 METHOD AND SYSTEM FOR REDUCING TRACE LENGTH AND CAPACITANCE IN A LARGE MEMORY FOOTPRINT Public/Granted day:2012-07-12
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