Invention Grant
- Patent Title: JFET ESD protection circuit for low voltage applications
- Patent Title (中): JFET ESD保护电路适用于低压应用
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Application No.: US13772105Application Date: 2013-02-20
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Publication No.: US08866200B2Publication Date: 2014-10-21
- Inventor: Robert Newton Rountree
- Applicant: Robert Newton Rountree
- Main IPC: H01L27/06
- IPC: H01L27/06 ; H01L27/02
Abstract:
An electrostatic discharge (ESD) protection circuit is disclosed. The circuit includes a first terminal (200), a first power supply terminal (Vdd), and a second power supply terminal (Vss). The circuit further includes a junction field effect transistor (JFET) having a current path coupled between the first terminal and the second power supply terminal. The JFET has a control terminal (202) coupled to the first power supply terminal.
Public/Granted literature
- US20130214333A1 JFET ESD PROTECTION CIRCUIT FOR LOW VOLTAGE APPLICATIONS Public/Granted day:2013-08-22
Information query
IPC分类:
