Invention Grant
US08866223B2 Process for manufacturing a power semiconductor device having charge-balance columnar structures on a non-planar surface, and corresponding power semiconductor device
有权
用于制造在非平面表面上具有电荷平衡柱状结构的功率半导体器件的工艺及相应的功率半导体器件
- Patent Title: Process for manufacturing a power semiconductor device having charge-balance columnar structures on a non-planar surface, and corresponding power semiconductor device
- Patent Title (中): 用于制造在非平面表面上具有电荷平衡柱状结构的功率半导体器件的工艺及相应的功率半导体器件
-
Application No.: US13434741Application Date: 2012-03-29
-
Publication No.: US08866223B2Publication Date: 2014-10-21
- Inventor: Alfio Guarnera , Mario Giuseppe Saggio , Ferruccio Frisina
- Applicant: Alfio Guarnera , Mario Giuseppe Saggio , Ferruccio Frisina
- Applicant Address: IT Agrate Brianza (MB)
- Assignee: STMicroelectronics S.R.L.
- Current Assignee: STMicroelectronics S.R.L.
- Current Assignee Address: IT Agrate Brianza (MB)
- Agency: Allen, Dyer, Doppelt, Milbrath & Gilchrist, P.A.
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/78 ; H01L29/06 ; H01L29/08 ; H01L29/739 ; H01L29/417 ; H01L29/872 ; H01L29/861 ; H01L29/10 ; H01L21/20 ; H01L21/324
Abstract:
An embodiment of a process for manufacturing a power semiconductor device envisages the steps of: providing a body of semiconductor material having a top surface and having a first conductivity; forming columnar regions having a second type of conductivity within the body of semiconductor material, and surface extensions of the columnar regions above the top surface; and forming doped regions having the second type of conductivity, in the proximity of the top surface and in contact with the columnar regions. The doped regions are formed at least partially within the surface extensions of the columnar regions; the surface extensions and the doped regions have a non-planar surface pattern, in particular with a substantially V-shaped groove.
Public/Granted literature
Information query
IPC分类:
