Invention Grant
- Patent Title: Repairable multi-layer memory chip stack and method thereof
- Patent Title (中): 可修复多层存储芯片堆栈及其方法
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Application No.: US13533977Application Date: 2012-06-27
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Publication No.: US08867286B2Publication Date: 2014-10-21
- Inventor: Ming-Hsueh Wu , Kun-Lun Luo , Chen-An Chen , Yee-Wen Chen
- Applicant: Ming-Hsueh Wu , Kun-Lun Luo , Chen-An Chen , Yee-Wen Chen
- Applicant Address: TW Hsinchu
- Assignee: Industrial Technology Research Institute
- Current Assignee: Industrial Technology Research Institute
- Current Assignee Address: TW Hsinchu
- Agency: Jianq Chyun IP Office
- Priority: TW100147476A 20111220
- Main IPC: G11C7/00
- IPC: G11C7/00

Abstract:
A repairable multi-layer memory chip stack wherein each of the memory chips of the chip stack includes a control unit, a decoding unit, a memory array module and a redundant repair unit comprising at least one redundant repair element. The decoding unit receives a memory address from an address bus, and correspondingly outputs a decoded address. The memory array module determines whether to allow a data bus to access the data of the memory array module corresponding to a decoded address in accordance with an activation signal of the control unit. The redundant repair element includes a valid field, a chip ID field, a faulty address field and a redundant memory. When the valid field is valid, the value of the chip ID field matches the ID code, and the value of the faulty address field matches the decoded address, the redundant memory is coupled to the data bus.
Public/Granted literature
- US20130155794A1 REPAIRABLE MULTI-LAYER MEMORY CHIP STACK AND METHOD THEREOF Public/Granted day:2013-06-20
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