Invention Grant
- Patent Title: Instruction breakpoints in a multi-core, multi-thread network communications processor architecture
- Patent Title (中): 指令断点在多核,多线程网络通信处理器架构中
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Application No.: US12976045Application Date: 2010-12-22
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Publication No.: US08868889B2Publication Date: 2014-10-21
- Inventor: Deepak Mital , Te Khac Ma , Narender Vangati , William Burroughs
- Applicant: Deepak Mital , Te Khac Ma , Narender Vangati , William Burroughs
- Applicant Address: US CA Milpitas
- Assignee: LSI Corporation
- Current Assignee: LSI Corporation
- Current Assignee Address: US CA Milpitas
- Agency: Smith Risley Tempel Santos LLC
- Agent Daniel J. Santos
- Main IPC: G06F9/38
- IPC: G06F9/38 ; G06F15/167 ; H04L12/873

Abstract:
Described embodiments provide a packet classifier for a network processor that generates tasks corresponding to each received packet. The packet classifier includes a scheduler to generate threads of contexts corresponding to tasks received by the packet classifier from a plurality of processing modules of the network processor. A multi-thread instruction engine processes instructions corresponding to threads received from the scheduler. The multi-thread instruction engine executes instructions by fetching an instruction of the thread from an instruction memory of the packet classifier and determining whether a breakpoint mode of the network processor is enabled. If the breakpoint mode is enabled, and breakpoint indicator of the fetched instruction is set, the packet classifier enters a breakpoint mode. Otherwise, if the breakpoint indicator of the fetched instruction is not set, the multi-thread instruction engine executes the fetched instruction.
Public/Granted literature
- US20110225394A1 INSTRUCTION BREAKPOINTS IN A MULTI-CORE, MULTI-THREAD NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE Public/Granted day:2011-09-15
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