Invention Grant
US08869005B2 Error correction in a stacked memory 有权
堆叠内存中的错误校正

Error correction in a stacked memory
Abstract:
Electronic apparatus, systems, and methods to construct and operate the electronic apparatus and/or systems include a stack of memory dies with user data and/or first level error correction data stored in a stripe across the memory dies. One such stack can include a second level error correction vault, such as a parity vault, to store parity data corresponding to the user data and/or first level error correction data. Additional apparatus, systems, and methods are disclosed.
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