Invention Grant
- Patent Title: Error correction in a stacked memory
- Patent Title (中): 堆叠内存中的错误校正
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Application No.: US13692812Application Date: 2012-12-03
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Publication No.: US08869005B2Publication Date: 2014-10-21
- Inventor: Joe M. Jeddeloh
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G11C29/00
- IPC: G11C29/00 ; H03M13/03 ; G06F11/10

Abstract:
Electronic apparatus, systems, and methods to construct and operate the electronic apparatus and/or systems include a stack of memory dies with user data and/or first level error correction data stored in a stripe across the memory dies. One such stack can include a second level error correction vault, such as a parity vault, to store parity data corresponding to the user data and/or first level error correction data. Additional apparatus, systems, and methods are disclosed.
Public/Granted literature
- US20130097471A1 ERROR CORRECTION IN A STACKED MEMORY Public/Granted day:2013-04-18
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