Invention Grant
- Patent Title: Memory system capable of increasing data transfer efficiency
- Patent Title (中): 能够提高数据传输效率的内存系统
-
Application No.: US13050565Application Date: 2011-03-17
-
Publication No.: US08874989B2Publication Date: 2014-10-28
- Inventor: Akihisa Fujimoto
- Applicant: Akihisa Fujimoto
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2010-219780 20100929
- Main IPC: G11C29/00
- IPC: G11C29/00

Abstract:
According to one embodiment, a host controller includes a command generator and detector. The command generator generates a command having a retransmission flag in an argument, and transmits the generated command to a memory device. The detector detects timeout if a response from the memory device cannot be recognized within a defined time. When transmitting an initial command, the host controller clears the retransmission flag and transmits the command. If the detector detects timeout, the host controller sets the retransmission flag, and retransmits the same command as the initial command to the device. If a normal response corresponding to the initial command or retransmitted command is received, the host controller recognizes that the command is correctly executed.
Public/Granted literature
- US20120079338A1 MEMORY SYSTEM CAPABLE OF INCREASING DATA TRANSFER EFFICIENCY Public/Granted day:2012-03-29
Information query