Invention Grant
- Patent Title: Recovery method for poor yield at integrated circuit die panelization
- Patent Title (中): 集成电路芯片成形率差的回收方法
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Application No.: US13166552Application Date: 2011-06-22
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Publication No.: US08877523B2Publication Date: 2014-11-04
- Inventor: George R. Leal
- Applicant: George R. Leal
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent Jonathan N. Geld; David G. Dolezal
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L23/544 ; H01L21/56 ; H01L21/683 ; H01L23/31 ; H01L23/00 ; H01L25/065
Abstract:
A method for making a packaged integrated circuit is provided. The method includes making a first panel of encapsulated die. In some embodiments, if a threshold number of die are not positioned in proper positions in the first panel, the die are separated from the first panel. The separated die are subsequently encapsulated in other panels of encapsulated die. Conductive interconnects can be formed over the other panels. The other panels are then separated into integrated circuit packages.
Public/Granted literature
- US20120329212A1 RECOVERY METHOD FOR POOR YIELD AT INTEGRATED CIRCUIT DIE PANELIZATION Public/Granted day:2012-12-27
Information query
IPC分类:
