Invention Grant
- Patent Title: Complementary junction field effect transistor device and its gate-last fabrication method
- Patent Title (中): 互补结场效应晶体管器件及其最终制造方法
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Application No.: US13626634Application Date: 2012-09-25
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Publication No.: US08877575B2Publication Date: 2014-11-04
- Inventor: Mieno Fumitake
- Applicant: Semiconductor Manufacturing International Corporation (Shanghai)
- Applicant Address: CN CN
- Assignee: Semiconductor Manufacturing International (Beijing) Corporation,Semiconductor Manufacturing International (Shanghai) Corporation
- Current Assignee: Semiconductor Manufacturing International (Beijing) Corporation,Semiconductor Manufacturing International (Shanghai) Corporation
- Current Assignee Address: CN CN
- Agency: Innovation Counsel LLP
- Priority: CN201110459296 20111231
- Main IPC: H01L21/337
- IPC: H01L21/337

Abstract:
The disclosure relates to a complementary junction field effect transistor (c-JFET) and its gate-last fabrication method. The method of fabricating a semiconductor device includes: forming a dummy gate on a first conductivity type wafer, forming sidewall spacers on opposite sides of the dummy gate, forming a source and a drain regions on the opposite sides of the dummy gate, removing the dummy gate, forming a first semiconductor region of a second conductivity type in an opening exposed through the removing the dummy gate, and forming a gate electrode in the opening.
Public/Granted literature
- US20130168741A1 COMPLEMENTARY JUNCTION FIELD EFFECT TRANSISTOR DEVICE AND ITS GATE-LAST FABRICATION METHOD Public/Granted day:2013-07-04
Information query
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