Invention Grant
US08877585B1 Non-volatile memory (NVM) cell, high voltage transistor, and high-K and metal gate transistor integration
有权
非易失性存储器（NVM）单元，高压晶体管和高K和金属栅极晶体管集成
- Patent Title: Non-volatile memory (NVM) cell, high voltage transistor, and high-K and metal gate transistor integration
- Patent Title (中): 非易失性存储器（NVM）单元，高压晶体管和高K和金属栅极晶体管集成
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Application No.: US13969180Application Date: 2013-08-16
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Publication No.: US08877585B1Publication Date: 2014-11-04
- Inventor: Asanga H. Perera , Cheong Min Hong , Sung-Taeg Kang
- Applicant: Asanga H. Perera , Cheong Min Hong , Sung-Taeg Kang
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent James L. Clingan, Jr.; Mary Jo Bertani
- Main IPC: H01L21/336
- IPC: H01L21/336
Abstract:
A method of making a semiconductor structure using a substrate having a non-volatile memory (NVM) portion, a first high voltage portion, a second high voltage portion and a logic portion, includes forming a first conductive layer over an oxide layer on a major surface of the substrate in the NVM portion, the first and second high voltage portions, and logic portion. A memory cell is fabricated in the NVM portion while the first conductive layer remains in the first and second high voltage portions and the logic portion. The first conductive layer is patterned to form transistor gates in the first and second high voltage portions. A protective mask is formed over the NVM portion and the first and second high voltage portions. A transistor gate is formed in the logic portion while the protective mask remains in the NVM portion and the first and second high voltage portions.
Information query
IPC分类:
