Invention Grant
US08877606B2 Low cost fabrication of double box back gate silicon-on-insulator wafers with subsequent self aligned shallow trench isolation 有权
低成本制造双盒背栅硅绝缘体上晶圆,随后自对准浅沟槽隔离

Low cost fabrication of double box back gate silicon-on-insulator wafers with subsequent self aligned shallow trench isolation
Abstract:
A semiconductor substrate structure for manufacturing integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate, the lower insulating layer formed from a pair of separate insulation layers having a bonding interface therebetween; an electrically conductive layer formed on the lower insulating layer; an insulator with etch stop characteristics formed on the electrically conductive layer; an upper insulating layer formed on the etch stop layer; and a semiconductor layer formed on the upper insulating layer. A scheme of subsequently building a dual-depth shallow trench isolation with the deeper STI in the back gate layer self-aligned to the shallower STI in the active region in such a semiconductor substrate is also disclosed.
Information query
Patent Agency Ranking
0/0