Invention Grant
US08878304B2 Fuse circuit for final test trimming of integrated circuit chip
有权
保险丝电路，用于集成电路芯片的最终测试修整
- Patent Title: Fuse circuit for final test trimming of integrated circuit chip
- Patent Title (中): 保险丝电路，用于集成电路芯片的最终测试修整
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Application No.: US13358242Application Date: 2012-01-25
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Publication No.: US08878304B2Publication Date: 2014-11-04
- Inventor: Li-Wen Fang , Chih-Hao Yang , An-Tung Chen
- Applicant: Li-Wen Fang , Chih-Hao Yang , An-Tung Chen
- Applicant Address: TW Chupei, Hsin-Chu
- Assignee: Richtek Technology Corporation, R.O.C.
- Current Assignee: Richtek Technology Corporation, R.O.C.
- Current Assignee Address: TW Chupei, Hsin-Chu
- Agency: Tung & Associates
- Priority: TW100220806 20111104
- Main IPC: H01L27/06
- IPC: H01L27/06 ; G11C29/00 ; H01L27/02
Abstract:
The present invention discloses a fuse circuit for final test trimming of an integrated circuit (IC) chip. The fuse circuit includes at least one electrical fuse, at least one control switch corresponding to the electrical fuse, and a resistant device. The electrical fuse is connected with the control switch in series between a predetermined pin and a grounding pin. The control switch receives a control signal to determine whether a predetermined current flows through the corresponding electrical fuse and breaks the electrical fuse. The resistant device is coupled between a bulk terminal and a source terminal to increase a resistance of a parasitic channel, such that an electrostatic discharge (ESD) protection is enhanced, and errors of final test trimming of an IC chip are avoided.
Public/Granted literature
- US20130113049A1 FUSE CIRCUIT FOR FINAL TEST TRIMMING OF INTEGRATED CIRCUIT CHIP Public/Granted day:2013-05-09
Information query
IPC分类:
